1. Field of the Invention
The present invention relates to a integrated circuit single port register.
2. Description of the Prior Art
The use of read/write control registers is common in the integrated circuit art. Referring to an illustrative case shown in FIG. 1, a D flip-flop 100 represents one of a bank of N flip-flops being accessed at a given time. The flip-flop 100 serves as the register latch for holding the desired register value and providing it to output node 106. In order to write data into the latch, a WRITE signal is asserted on line 108. This signal is typically supplied to a plurality of control logic gates similar to the illustrated gate 102, and hence may be referred to as a "generic" WRITE signal. In addition, an ADDRESS signal is asserted on line 109 for the particular register bank selected, and hence this signal is referred to as a "unique" ADDRESS. The logical combination of these signals is supplied from AND gate 102 via line 111 to the clock input of flip-flop 100. Therefore, the data input present on a given conductor of read/write data bus 107 (either logic "0" or alternatively logic "1") is latched into the flip-flop 100 at the fall (high-to-low transition) of the WRITE signal from 102. The latched signal value is supplied via the Q output as the register value to other circuitry (not shown).
In many cases, it is desired to read out the value of the register from the same data bus that supplied the data to the register. This is useful, for example, in performing diagnostic testing of the logic circuitry. Therefore, a read output may be obtained by the inclusion of tri-state buffer 101, being a representative one of a bank of N buffers that supplies the signal from representative output node 106 to a read data bus 105. This read data bus is connected to the write data bus 104 to form a read/write data bus 107. Note that the read data bus is often buffered by means of a read buffer (not shown) before being combined with the write data bus. Similarly, the write data bus is often buffered by means of a write buffer (not shown) before it reaches the D input. These buffers are activated by control lines (also not shown) as appropriate during read and write operation. Note that the tri-state output buffer 101 is controlled by line 112 from AND gate 103, which activates the buffer 101 when both an address unique to the register is supplied on line 109, and a generic read signal is supplied on line 110.